#MATLAB SIMULINK CLOCK SIMULATOR#
Also note, that even though we have set Ts=Tout=8ns in Simulink, the Simulink engine does not know how the HDL simulator will perform its delta-time iterations. Hence Simulink samples the previous state of output at 16ns. In order to better understand why this delay occurs, we have captured a snapshot of the HDL simulator waveform (with delta-time delays and events expanded), when the simulation was run with Tout=8ns:Īt 16ns, the output parity_out1 within the HDL simulator still holds its previous state, since the output is only slated to change at rising edge of clock. However, the output mismatch seen on the Simulink scope is for 24ns.
#MATLAB SIMULINK CLOCK CODE#
The Verilog code is driven such that the module is reset for the first 16ns. In the Verilog code paritychecker_clk_driver.v note how the positive edge of the clock (which is the active edge) has purposely been offset by half its period so as avoid a potential race condition. In order to avoid such race conditions it is essential that Simulink values are not driven/ sampled at the same time as an active clock edge in HDL.
Thus, if the Simulink values are driven/ sampled at the same time as an active clock edge in the HDL, there is a race condition. On the other hand, the HDL simulator does not make any guarantees as to the order of a value change versus some other blocking signal assignment. It is important to understand that the Simulink engine does not work in delta-time cycles and hence Simulink queries the output port of the HDL Cosimulation block at definite discrete time intervals. Effect of Clocks Driving an HDL Module and Race Conditions We will discuss this in detail later in the example. The initial values of the two outputs do not match up due to the reset logic used within HDL (which Simulink does not know about and does not incorporate in its algorithm). You will notice that the outputs from the Simulink algorithm match the outputs obtained from the HDL Cosimulation block (labeled as 2 in the image), except for the first 24ns (labeled as 1 in the image). Observe the settings within the HDL Cosimulation block's Ports paneĭouble-click on the HDL Cosimulation block to edit the cosimulation parameters. Use the startup command provided within the model for this.Ģ. Hence the module is capable of updating its output at a maximum rate of 8ns, that is, at every rising edge of clock.īefore running the model, you must first launch the HDL simulator. The clock has a period of 8ns, and is set up such that its first rising edge occurs at 4ns. Reset is held high for the first 16ns and is low thereafter.
#MATLAB SIMULINK CLOCK DRIVER#
Note that the clock and reset inputs for the design under test are generated within the HDL driver module, ( paritychecker_clk_driver.v).
The clickable annotations can be used to change the sample time of the HDL Cosimulation block's output port (Tout). The model showcases how the Simulink sampling rate affects cosimulation with an HDL module. A scope is used to view their outputs and compare results. I take solace in the fact that he used HgTransform to do this fancy animation, and that functionality did not exist when I started.In the model we use an 8-bit counter to provide input data to the HDL code through the HDL Cosimulation block, and its equivalent Simulink algorithm. Mine just flipped the card images in place, but his flips them through the air! I have to say that there is an ever increasing level of sophistication in these clocks since I made mine six years ago. I recently saw people “ooohing” and “aaahing” in one of the offices while looking at Brendan’s clock. This is a good chance for them to show-off and refine their MATLAB skills. One of the first challenges the people joining this group have when coming to The MathWorks is to write a clock in MATLAB. I recently changed jobs and offices within the MathWorks and am now sitting within the Engineering Devlopment Group (the friendly people that answer your tech support questions on the phone or by e-mail). The file submission referenced in this post is no longer available on File Exchange.